Memory Block (Page)

Memory Block (Page)

A memory block (also called a page in NFC Forum Type 2 tags) is the smallest addressable unit of NFC tag memory. When an NFC reader issues a READ or WRITE command, it addresses data at the block level — you cannot read or write individual bytes within a block. Block size and addressing conventions vary by tag type, directly affecting how efficiently user memory can be utilized.

Block Sizes by Tag Type

Type 2 Tag Page Structure

For NTAG and MIFARE Ultralight chips, memory is organized as a linear array of 4-byte pages. A READ command returns 4 consecutive pages (16 bytes) starting from the specified page address. A WRITE command writes exactly one page (4 bytes) at a time.

The page structure has specific regions:

• Pages 0-1: Contain the 7-byte UID and manufacturer internal bytes. These pages are factory-programmed and read-only.
• Page 2: Static lock bits and internal configuration. The lock bits control write access to pages 3-15.
• Page 3: Capability container (CC). Describes NDEF version, memory size, and read/write access conditions.
• Pages 4 through N: User memory for storing NDEF messages and application data.
• Pages N+1 onward: Dynamic lock bits (controlling write access to the user memory region) and chip configuration pages.

Read Alignment Considerations

Because the READ command returns 16 bytes (4 pages) regardless of how much data you need, reading a single byte still retrieves an entire 16-byte block. Similarly, writing a single byte requires reading the containing page, modifying the byte, and writing back the full 4-byte page. This read-modify-write pattern must be handled carefully to avoid corrupting adjacent data within the same page.

Block Addressing in Type 5 Tags

NFC-V / Type 5 tags based on ISO 15693 use similar 4-byte blocks but with different command sets (ReadSingleBlock, WriteSingleBlock, ReadMultipleBlocks). Some chips like the ST25DV support extended block addressing (2-byte block numbers) to address memory beyond 256 blocks (1 KB).