Wafer

What Is a Wafer?

A waferwaferSilicon disc containing hundreds of fabricated NFC IC diesView full → is a thin, circular disc of highly purified semiconductor silicon on which hundreds to thousands of NFC IC dies are fabricated simultaneously using photolithographic processes. Wafers are the starting material for all NFC chip production, manufactured at semiconductor foundries operated by companies like NXP Semiconductors, Infineon, and STMicroelectronics. The wafer represents the highest-volume, most cost-efficient stage of NFC chip manufacturing.

Wafer Specifications

Modern NFC chip wafers conform to standardized dimensions:

A single 200 mm wafer can yield over 5,000 NTAG 213 dies, making wafer-level fabrication extremely cost-effective for high-volume NFC tagNFC tagPassive unpowered device storing data, powered by reader's RF fieldView full → production. The larger 300 mm wafers used by advanced foundries can double the output per wafer.

Wafer Fabrication Process

NFC chips are fabricated using standard CMOS (Complementary Metal-Oxide-Semiconductor) process technology. The key fabrication steps include:

1. Oxidation. A thin layer of silicon dioxide is grown on the wafer surface to provide electrical insulation.
2. Photolithography. Circuit patterns are transferred to the wafer surface using UV light and photoresist masks, defining transistors, interconnects, and memory cells.
3. Ion implantation. Dopant atoms are implanted into the silicon to create p-type and n-type semiconductor regions for transistor formation.
4. Metal deposition. Aluminum or copper interconnect layers are deposited and patterned to wire together the transistors, EEPROM cells, and bond pads.
5. Passivation. A protective layer is applied over the completed circuitry.

NFC chips typically use mature process nodes (90-180 nm) rather than the leading-edge nodes used for processors and GPUs. This mature technology is well-characterized, highly reliable, and cost-effective for the relatively simple circuitry in NFC ICs.

Wafer Testing

Before dicing, every die on the wafer undergoes electrical testing using automated probe stations. Probe needles contact the die's bond pads and run a test program that verifies:

• RF front-end functionality (resonant frequency, power harvesting)
• EEPROM read/write operations across all memory blocks
• Logic controller protocol compliance
• Cryptographic engine operation (for security chips)
• UID programming and readback

Failed dies are marked with an ink dot and excluded during the subsequent dicing and bonding stages. Typical wafer yields for mature NFC chip designs exceed 95%, meaning fewer than 5% of dies are defective.

From Wafer to Inlay

After testing, the wafer is diced into individual dies, which are then bonded to NFC antennas to create inlays. The transition from wafer to inlay is where chip manufacturing intersects with antenna design and tag converting, bridging semiconductor fabrication and NFC product assembly.

Wafer Supply Chain

NXP Semiconductors is the dominant NFC chip manufacturer, supplying the NTAG, MIFARE, ICODE, and DNA product families. Other notable manufacturers include Infineon (SECORA), STMicroelectronics (ST25 series), and Sony (FeliCa). The wafer supply chain has become increasingly important as NFC deployment volumes have grown, with wafer allocation and lead times directly affecting tag availability and pricing in the market.