Memory & Data

Write Endurance

The number of write/erase cycles an NFC chip's EEPROM can sustain before reliability degrades. Typical NFC chips guarantee 100,000 write cycles. Higher-end chips may support 1,000,000+ cycles.

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Write Endurance

Write endurance is the number of write/erase cycles an NFC chip's EEPROM memory cells can sustain before the probability of bit errors increases beyond acceptable levels. Each write cycle stresses the floating-gate oxide layer, gradually degrading the cell's ability to reliably store charge. NFC chip manufacturers specify a guaranteed minimum write endurance to set design boundaries for applications that update tag data in the field.

Specifications by Chip

Chip Write Endurance Memory Technology
NTAG 213 / 215 / 216 100,000 cycles EEPROM
NTAG 424 DNA 200,000 cycles EEPROM
MIFARE DESFire EV3 500,000 cycles EEPROM
ICODE SLIX2 100,000 cycles EEPROM
ST25DV 1,000,000 cycles EEPROM

These figures represent the guaranteed minimum across all memory cells at the specified operating temperature range. Individual cells may survive significantly more cycles, but the guarantee ensures no cell fails before the rated count under worst-case conditions.

Write Cycle Mechanics

A single write cycle on an EEPROM cell consists of two phases:

  1. Erase: A high voltage (~15V, generated by an on-chip charge pump) is applied to pull electrons off the floating gate through Fowler-Nordheim tunneling.
  2. Program: A different high voltage configuration injects electrons onto the floating gate to store a 0 bit.

Each erase/program cycle creates minor damage to the thin oxide separating the floating gate from the substrate (oxide stress, trap generation). Over many cycles, this damage accumulates until the oxide can no longer reliably hold charge — manifesting as data retention degradation or outright bit failures.

Practical Calculations

For most NFC applications, write endurance is not a limiting factor:

  • Static tag (URL, vCard): Written once during manufacturing, then read-only in the field. Total write cycles: 1. Write endurance is irrelevant.
  • Rewritable marketing tag: Updated weekly with new campaign URLs. At 52 writes per year, a 100,000-cycle tag lasts ~1,923 years.
  • Counter-based loyalty tag: Incremented on every customer tap. If a busy retail location processes 100 taps per day, a 100,000-cycle tag lasts ~2.7 years. For this use case, chips with higher endurance (DESFire at 500K, ST25DV at 1M) are recommended.
  • IoT sensor tag with continuous writes: Dual-interface tags writing sensor data every minute (525,600 writes/year) would exhaust 100K cycles in ~2 months. These applications require 1M+ cycle chips or wear-leveling strategies.

Write Endurance vs Data Retention

Write endurance and data retention are inversely coupled. A cell that has undergone 90,000 out of 100,000 rated cycles will have shorter data retention than one written only a few times. When both parameters are critical, engineers must account for the combined effect — a tag written near its endurance limit may not meet the 10-year retention guarantee under the same temperature conditions as a freshly written tag.

Related Terms

Related Guides

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The NFC glossary is a comprehensive reference of technical terms, acronyms, and concepts used in Near Field Communication technology. It is designed for developers, product managers, and engineers who work with NFC and need clear definitions of terms like NDEF, APDU, anti-collision, and ISO 14443.

Each glossary term is cross-referenced with related NFC chips, standards, and other terms. For example, the term 'AES-128' links to chips that support AES encryption (NTAG 424 DNA, DESFire EV2/EV3), and the term 'ISO 14443' links to all chips compliant with that standard.

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